HLK-LD6002C device has integrated 2 transmit and 2 receive channels, IQ down-conversion mixers, a RF VCO, a Fractional-N PLL, frequency tripler, built-in digital signal processing units, including FIR, FFT and other radar signal processing function blocks. The device includes an ARM® Cortex®-M3 Core based processor subsystem, which is responsible for radio chip configuration, control, calibration and data communications. The device is provided with a complete platform including reference design, software drivers, API guides and user documentations. The device also supports cascade-mode operation for applications that need higher accuracy and long range.

Product Features

Integrated PLL, Transmitter, Receiver, Baseband and ADCs
Operating Frequency: 57 to 64GHz
2-Transmit, 2-Receive Channels
Ultra-Accurate Chirp (Timing) Engine Based on Fractional-N PLL
Tx Power @ Single Channel: 12dBm
57 to 65GHz Phase Noise@1MHz offset: - 91dBc/Hz
Rx Noise Figure: 11dB
RF Built-in self-test (BIST) module, Self-calibrated System Across Frequency and Temperature
ARM® Cortex®-M3 Core
Built-in Digital Signal Process, including FIR, FFT and etc.
Built-in FMCW Chirp generation
Available IOs:

--- 1 SPI Channels

--- 1 CAN2.0/CAN-FD

--- 3 UARTs

--- 1 I2Cs

--- Interface for analog IF output

Power management with low power mode
Digital I/O voltage 3.3V
Clock Source

--- 50.0MHz Oscillator or Crystal

--- Support external 32.768KHz crystal

--- Internal RC Oscillator, 32KHz +/- 20%

Easy hardware design with 0.5mm pitch, 113-pin and 6.75mm x 6.75mm x 0.49mm fanout BGA package for small formfactor size

Applications

Respiratory rate monitoring
Human persistence monitoring
Gesture recognition
Low power carpark monitoring

System Block Diagram

diagram

Specifications

Signal Name	Signal description	Max Ratings		Unit
Signal Name	Signal description	Min	Max	Unit
RF power	RF power	0	1.45	V
VDD	Digital 1.2V supply	0	1.4	V
VDD12	Internal 1.2V LDO output	0	1.4	V
AVDD18_PLL	Internal PLL Power supply	0	2.75	V
AVDD18_PLL_VCO	Internal VCO Power	0	2.75	V
AVDD18_BB1	Internal Baseband1 Power	0	2	V
AVDD18_BB2	Internal Baseband2 Power	0	2	V
VDD33	Analog 3.3V Power	0	3.63	V
DVDD33	Digital 3.3V Power	0	3.63	V
CLKP, CLKN	Input ports for reference crystal	-0.5	2	V
Clamp current	Limit clamp current through the internal diode protection of the I/O	-20	20	mA
T J	Operating junction temperature range	-40	125	°c
T STG	Storage temperature range after soldered onto PC board	-55	150	°c

(1) Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods of time may affect device reliability and lifetime

Module Block